Oxide-nitride-oxide (ONO) stacks are widely used as a charge storing layer in non-volatile memory (NVM) transistors, such as in silicon-oxide-nitride-oxide-silicon (SONOS) or metal-oxide-nitride-oxide-silicon (MONOS), and as an isolation layer between a floating gate and control gate in split gate flash NVM transistors. NVM transistors are programmed by applying a positive bias between a control gate and a body contact of the transistor. The positive bias causes electrons from source and drains regions of the transistor to tunnel through the lower oxide layer of the ONO stack and become trapped in the nitride layer. This results in an energy barrier between the drain and the source, raising the threshold voltage (VT) of the transistor to a programmed threshold voltage (VTp). The NVM transistor is erased or returned to an erased threshold voltage (VTe) by applying a negative bias between the control gate and body contact.
The difference between the programmed threshold voltage (VTp) and the erased threshold voltage (VTe) of the transistor, is known as a VT window and is the typically reduced over time due to the loss of charge stored in the nitride layer. This loss can be due to several mechanisms of charge leakage. The VT window at the end of life of the part depends on the window at the beginning of life and the rate of decay with time. Thus, in order to meet a specified operating life, e.g., 17 years, the transistor must meet a specified minimum beginning of life (BOL) VT window, e.g., 3.0VDC.
The BOL VT window depends on the amount of charge stored in the nitride in the program and erase states which in turn depend on how efficiently electrons or holes are injected into the nitride layer during program and erase. An important figure of merit used to characterize quality of the ONO stack is the program/erase efficiency of the NVM transistors. By program/erase efficiency it is meant the biasing voltage and time for which it must be applied to program or erase the NVM transistor. Conventional methods of testing NVM transistors include testing a completed, packaged device, which can take weeks after deposition of an ONO stack. Thus, any problem with composition of one or more layers of the ONO stack due to a malfunction in the process or tool, even one that might be corrected in fabrication, will not be discovered for weeks resulting in lowered yield of devices meeting specified parameters and substantial loss of revenue.